This invention generally relates to semiconductor devices, and more specifically to methods and structures that improve electrostatic discharge (ESD) and failure robustness in modern integrated circuit (IC) devices.
As IC design geometries continue to shrink, susceptibility to ESD damage increases. An IC may be exposed to ESD from many sources, such as automated assembly equipment and human body contact. A major source of ESD exposure for ICs is from the human body, For instance, a charge of about 0.6 xcexcC can be induced on a human body with a body capacitance of 150 pF. When the charged human body comes in contact with the input or output pins of an IC, a discharge through the IC may result and cause damages to the IC. Such a discharge event is typically simulated using a Human Body Model (HBM), which, in one example, includes a 100-150 pF capacitor discharged through a switching component and a 1.5 kOhm series resistor into the IC.
A discharge similar to the HBM event can also occur when the IC comes in contact with a charged conductive object, such as a metallic tool or fixture. This is typically modeled by a so called machine model (MM). In one example, the MM includes a 200 pF capacitor discharged directly into the IC. The MM is sometimes referred to as the worst-case HBM.
The transfer of charge from the IC is also an ESD event. The IC may become charged, for example, from sliding down a feeder in an automated assembler. If it then contacts a metal insertion head or another conductive surface, a rapid discharge may occur from the device to the metal object. This event is typically modeled by a Charged Device Model (CDM). Because the IC itself becomes charged in a CDM event, and discharges to ground, the discharge current flows in the opposite direction in the IC as compared to that of an HBM event or MM event. Although the duration of the CDM discharge is typically very short, often less than one nanosecond, the peak current can reach several tens of amperes. Thus, the CDM discharge can be more destructive than the HBM event for some ICs.
Many commonly used ICs contain elements, such as transistors, resistors, capacitors and interconnects, that can fail when an ESD event occurs thereby affecting the quality, reliability, yield, delivery, and cost of ICs. As a result, IC product failure from ESD is an important concern in the semiconductor microelectronics industry; and undustry standards require that IC products withstand a minimum level of ESD. To meet this requirement, ESD protection circuitry is generally built into the input, output, and/or power supply circuits of an IC.
The ability to produce workable ESD protection structures depends upon the interrelationship of the IC""s topology, the design layout, the circuit design, and the fabrication process. Various circuit designs and layouts have been proposed and implemented for protecting ICs from ESD. One common ESD protection scheme used in metal-oxide-semiconductor (MOS) ICs relies on parasitic bipolar transistors associated with MOS devices in the ESD protection circuitry, such as an n-type MOS (NMOS) device whose drain is connected to the pin to be protected and whose source is tied to ground. The protection level or failure threshold can be adjusted by varying the length of the NMOS device.
One method used to improve ESD protection offered by the MOS device is to bias the substrate of an ESD protection circuit on an IC. Substrate biasing can be effective at improving the response of a single or multi-finger MOS transistor that is used to conduct an ESD discharge to ground. Nevertheless, substrate biasing can also cause the threshold voltages of other devices in the IC to change from their nominal values and thus affect device operation. In addition, substrate biasing under steady-state conditions generates heat and increases power losses.
Another common approach to improve ESD protection is to add an ESD implant in the MOS device in the ESD protection circuitry. However, conventional ESD implants, such as deep p-type implants under an n-type source or drain region, can significantly increase the input or output junction capacitance and source-drain resistance, degrading circuit performance. Furthermore, the addition of the ESD implant requires additional process steps, thereby increasing manufacturing costs, time and room for error.
Therefore, there is a need for an ESD protection circuitry offering sufficient ESD protection without the problems of heating, power losses, and device malfunction associated with existing substrate biasing circuits. There is also a need for an ESD protection circuitry that offers sufficient ESD protection without extra manufacturing steps. Furthermore, there is a need for an ESD protection circuitry that provides sufficient ESD protection without the degradation in circuit performance associated with conventional approaches.
The present invention meets the above need by providing a simple ESD protection structure for use in an ESD protection circuitry and methods of making the ESD protection structures. The ESD protection structure can be used to provide sufficient ESD protection to most complementary MOS (CMOS) ICs without the trade-offs of conventional approaches. In one aspect of the present invention, the ESD protection structure constitutes a reliable discharge path and is fabricated on a substrate without the need for processing steps other than those required for fabricating the CMOS ICs.
In one embodiment of the present invention, in an integrated circuit fabricated on a semiconductor substrate, an ESD protection circuit protects one or more semiconductor devices in the integrated circuit from damage caused by an ESD pulse. The ESD protection circuit comprises a first diffusion region having a first conductivity type formed at a surface of the semiconductor substrate. One or more contacts in the first diffusion region provides connection of the first diffusion region to the region where the ESD pulse accumulates. The ESD protection circuit also comprises a second diffusion region formed at the surface of the semiconductor substrate. The second diffusion region is adjacent to the first diffusion region and is of a second conductivity type opposite to the first conductivity type.
In an example of the present invention, the first diffusion region is the n-type source or drain region of one or more NMOS transistors. The source or drain region has one or more notches at its edges, or holes or openings in the middle of it, and the second diffusion region, a p-type diffusion region, occupies the notches or holes or openings of the n-type source or drain region. As a result, a pn junction is formed between the first diffusion region and the second diffusion region. In response to an ESD pulse received at the first diffusion region through the contacts, the pn junction breaks down earlier than the source or drain junctions in the protected semiconductor devices. The breakdown of the pn junction triggers one or more parasitic bipolar transistors associated with the one or more NMOS transistors, causing discharge current to flow through the bulk of these transistors thereby discharging the ESD pulse.
Alternatively, the first diffusion region can be the p-type source or drain region of one or more PMOS transistors and the second diffusion region, being n-type, occupies the notches or holes or openings of the p-type source or drain region. Again, a pn junction is formed between the first diffusion region and the second diffusion region and operates to trigger one or more parasitic bipolar transistors associated with the one or more PMOS transistors, discharging the ESD pulse received at the first diffusion region.
The present invention also provides several technical advantages. One important technical advantage of the present invention is that it provides sufficient protection from various ESD sources. For instance, the ESD protection circuitry of the present invention is effective to protect the IC from the HBM, MM or CDM and other ESD events. The present invention also offers better scalability and layout efficiency.